Moore's law has affected the microchip world where many system applications have demanded more functionality and high performance in ever-smaller form factors. The manufacturing cost also has increased since the first process technology of the late 1950's. As shown in FIG. 1, connecting signals to a microchip 11 from package level requires some chip area for metal bond pads 10. The pad size (area) must satisfy requirements of the packaging process and the minimum possible bonding wire diameter. In order to prevent mechanical damage and thermal stress in each corner of the microchip, dummy pads such as 12 are typically provided.
These kinds of factors require chip area to be sacrificed for bond pads. Along with the bond pad area, some space is provided between the pad and the chip edge to avoid cracks near the pad.
Wire bonding requires electrical connection to the pad, and thus a large enough metal pad area to permit safely connecting the bonding wire to the pad. This results in relatively large capacitive and inductive loading from the metal pad area and the bonding wire itself. Although internal transistor sizes have been steadily reduced by innovations in process technology, the pad size and bonding wire diameter have not kept pace with the shrink ratio of the transistors. Due to this unbalanced trend, the relative influence of the capacitive and inductive loading effect of the pad and bonding wire is increasing seriously. This is generally detrimental, and particularly so for high-speed applications.
It is therefore desirable to provide for reducing the capacitive and inductive loading, and the chip area sacrifices, associated with prior art integrated circuit chip connections at the package level.